1. Field of the Invention
The present invention relates to a circuit for protecting integrated circuits from electrostatic discharge, and more particularly, to an electrostatic discharge protection circuit having a trigger circuit for triggering a silicon controlled rectifier (SCR) circuit which uses the SCR latchup effect present in CMOS processes to divert the electrostatic discharge current pulse away from sensitive integrated circuit structures.
2. Description of the Prior Art
Electrostatic discharge (ESD) causes substantial damage to integrated circuits during and after the chip manufacturing process. ESD events are particularly troublesome for CMOS chips because of their low power requirements and extreme sensitivity. This ESD phenomena has been widely studied. For example, Khurana et al. noted in an article entitled "ESD On CHMOS Devices--Equivalent Circuits, Physical Models and Failure Mechanisms", IEEE/International Reliability Physics Symposium, 1985, pp. 212-223, that on CMOS outputs the n-channel device absorbs most of the ESD and is very fragile, while Duvvury et al. similarly noted in an article entitled "ESD Phenomena and Protection Issues in CMOS Output Buffers", IEEE/International Reliability Physics Symposium, 1987, pp. 174-180, that the avalanche conduction of the n-channel devices absorbs the majority of the ESD. As a result, prior art ESD protection circuits have included one or more n-channel FETs for dissipating current created by an ESD event.
On-chip ESD protection circuits for CMOS chips is essential. Generally, such circuits require a high failure threshold, a small layout size and a low RC delay so as to allow high speed applications. However, such ESD protection circuits have heretofore been difficult to design.
Previously, resistors and diodes were used in CMOS ESD protection circuits, but such resistors and diodes have been gradually replaced by three-layer devices such as field-oxide MOSFETs, gate-oxide MOSFETs and parasitic npn or pnp bipolar junction transistors (BJTs) in CMOS technologies. Others have used a parasitic four-layer pnpn device known as a silicon controlled rectifier (SCR) to protect a chip against the damages caused by ESD events. For example, Avery reported in an article entitled "Using SCR's as Transient Protection Structures in Integrated Circuits" 1983 EOS/ESD Symp Proc., EOS-5, pp. 177-180, that SCRs may be used in ESD protection circuits for bipolar technologies. As described by Avery, an SCR is typically triggered by a positive transient when it exceeds the collector-base breakdown potential of the npn transistors. Relatively recently, the parasitic lateral SCR device has also been used in CMOS on-chip protection circuits. For example, Rieck et al. describe in an article entitled "Novel ESD Protection for Advanced CMOS Output Drivers", 1989 EOS/ESD Symp. Proc., EOS-11, pp. 182-189, that latching devices such as SCRs may be useful for protecting NMOS transistors in CMOS output drivers by increasing the failure voltage of inherently weak drivers. Rountree et al. further describe in an article entitled "A Process-Tolerant Input Protection Circuit For Advanced CMOS Processes" 1988 EOS/ESD Symp Proc., EOS-10, pp. 201-205, that lateral SCRs which are process-tolerant for advanced CMOS processes may be used to protect circuitry from ESD events.
Due to its high current sinking/sourcing capability, very low turn-on impedance, low power dissipation, and large physical volume for heat dissipating, parasitic lateral SCR devices have been recognized in the prior art as one of the most effective elements in CMOS on-chip ESD protection circuits. However, there is a major disadvantage with using the parasitic SCR device in ESD protection circuits in that the SCR device has a high trigger voltage. To perform ESD protection, the trigger voltage of an ESD protection circuit must be less than the voltage which could damage the input buffer or output driver. As described by Rountree et al., the typical trigger voltage of a parasitic lateral SCR device in the ESD protection circuits fabricated by the advanced 1 .mu.m CMOS process with lightly doped drain and silicided diffusion is about 50 volts if the space from its anode to cathode is 6 .mu.m. Unfortunately, with such a high trigger voltage the lateral SCR device cannot be used as the only protection element. As a result, a field-planted diode and a diffusion resistor ("secondary protection" elements) have been incorporated with the lateral SCR device in the protection circuit to provide improved ESD protection.
To avoid the use of such "secondary protection" elements, Rieck et al. and others have attempted to reduce the trigger voltage of the parasitic lateral SCR devices. As described by Chatterjee et al., for example, in an article entitled "A Low-Voltage Triggering SCR For On-Chip ESD Protection at Output and Input Pads" Proc. 1990 Symp. VLSI Tech., pp. 75-76, one method is to integrate a low breakdown voltage short-channel NMOS FET within the lateral SCR device to form a "LVTSCR" structure which has a good tunable trigger voltage in the range of 10-15 volts. However, those skilled in the art will appreciate that it may not be generally feasible to combine the NMOS FET and the lateral SCR device in this manner. As described in the aforementioned article to Rieck et al., the other method is to add a "NLCS" mask to make a recessed field implant in the lateral SCR device in order to lower its trigger voltage. Experimental results have shown that the minimum breakdown voltage of such an SCR defined and measured at the initial current flow of 1 .mu.A is lowered to 9 volts, while its corresponding trigger voltage to initiate the latching state is about 20 volts. However, this approach is generally impractical because of manufacturing control issues.
FIGS. 1(a) and 1(b) illustrate an ESD protection circuit having an SCR structure similar to that described in the aforementioned article to Chatterjee et al. FIG. 1(a) illustrates the circuit diagram, while FIG. 1(b) illustrates the corresponding substrate. The ESD protection device illustrated in FIGS. 1(a) and 1(b) includes an SCR device 10 comprising cross-coupled bipolar PNP transistor 12 and NPN transistor 14 connected between an input/output pad 15 on the integrated circuit 16 to be protected and the chip ground of the integrated circuit 16. The resistance R.sub.s of the p-substrate in which the SCR 10 is formed is illustrated along with the well resistance R.sub.w, which establishes a small threshold current which must be reached before the SCR device 10 may be activated. As illustrated in FIGS. 1(a) and 1(b), an NMOS trigger FET 18 is further provided for lowering the triggering voltage of the SCR 10 to the breakdown voltage of the trigger FET 18.
The ESD protection circuit illustrated in FIGS. 1(a) and 1(b) thus requires that a trigger device such as NMOS trigger FET 18 be subjected to junction breakdown conditions before the SCR 10 may be activated. In particular, enough current must flow through the NMOS trigger FET 18 to initiate latchup by SCR device 10. However, since the circuitry 16 being protected can also experience junction breakdown, there is no mechanism in the circuit of FIG. 1 to insure that enough current will flow through the NMOS trigger FET 18 to initiate latchup. Furthermore, there is no assurance that device breakdown effects such as bipolar snapback will result in all the ESD current being absorbed by the output circuitry rather than the illustrated ESD protection structure.
During operation of the circuit of FIG. 1, the NMOS trigger FET 18 operates in the junction breakdown condition to pull current through the well resistor R.sub.w. This breakdown voltage is approximately equal to the breakdown voltage of the circuitry to be protected, and, as just noted, it is impossible in such a circuit to insure that the circuitry 16 to be protected will not conduct significant amounts of current due to device breakdown. It is also not possible to ensure that the circuitry 16 to be protected will not "steal" the current from the SCR device 10, thereby inhibiting the SCR device 10 from latching up and absorbing the majority of the ESD event energy.
FIGS. 2(a) and 2(b) illustrate an ESD protection circuit of the type illustrated in FIG. 1 except that an NMOS FET 20 is added for lowering the breakdown voltage by floating the gate of NMOS trigger FET 18 when chip power V.sub.DD is low. FIG. 2(a) illustrates the circuit diagram, while FIG. 2(b) illustrates the corresponding substrate. As illustrated, the NMOS FET 20 is responsive to V.sub.DD to float the gate of the NMOS trigger FET 18 when the circuitry 16 to be protected is not powered up. Once powered up (V.sub.DD goes high), the gate of the trigger FET 18 is grounded so as to minimize the effect of the protection circuitry on the operation of the circuitry 16 to be protected. However, in the circuitry of FIGS. 2(a) and 2(b), latching by the SCR device 10 still relies upon the breakdown of the NMOS trigger FET 18 for initiation of latchup and is still susceptible to current "stealing" by the circuitry 16, which will also have floating gates. Thus, the aforementioned problems have not been overcome by the circuit of FIG. 2.
Accordingly, an ESD protection circuit is still desired which will enable the SCR to latch independent of the breakdown effects of the NMOS trigger FET. The present invention has been designed to meet this need.